The present invention relates to a driver circuit for transmitting a signal by switching the direction of the current which flows on a pair of transmission lines and, more particularly, to a driver circuit used for an interface for transmitting a small-amplitude signal at a high speed.
Recently, attention has been attracted on an LVDS (Low Voltage Differential Signal) interface for transmitting a small-amplitude differential signal.
FIG. 12 shows the structure of an LVDS interface. A driver 1 and a receiver 2 is combined by an upward transmission line 3 and a downward transmission line 4 each having a characteristic impedance of 50 .OMEGA.. The transmission lines 3, 4 are terminated by a resistor 5 of 100 .OMEGA. at the input end of the receiver 2. The driver 1 drives a current of about 3 mA and produces a voltage of about 300 mV at the terminating resistor 5.
The upward transmission line 3 and the downward transmission line 4 constitute what is called balanced transmission lines which have the same electrical characteristics. The leading characteristic of the LVDS interface is that one signal is transmitted through these balanced of transmission lines. The driver 1 generates a differential signal which produces a potential difference between the upward transmission line 3 and the downward transmission line 4 on the basis of a signal input from an input terminal 6. In contrast, the receiver 2 converts the differential signals generated between the upward transmission line 3 and the downward transmission line 4 into a signal of a CMOS level and outputs this signal from an output terminal 7.
The principle of the LVDS interface is that a signal is transmitted by generating a signal voltage at the terminating resistor 5 by applying a signal current Is which is generated on the side of the driver 1 to a loop which is constituted by the balanced transmission lines of the upward transmission line 3 and the downward transmission line 4 and the terminating resistor 5 on the side of the receiver 2. The signal "1" or "0" is identified by switching the direction of the flow of the signal current Is. According to this structure, since the signal currents Is flowing on the upward transmission line 3 and the downward transmission line 4 have the same size but flow in the opposite directions, the magnetic fields generated by the entire balanced transmission lines are cancelled by each other. Owing to this characteristic, the noise produced by a change in the current of the transmission system is small, and the interference between the transmission lines of the adjacent ports and the interference of simultaneous switching between LSIs are small. Accordingly, the LVDS interface is suitable for high-speed signal transmission.
FIG. 13 shows an example of a conventional LVDS driver circuit.
In FIG. 13, the symbols N100 and N101 denote a pair of NMOS transistors as current switching elements on the high-potential side, N102 and N103 a pair of NMOS transistors as current switching elements on the low-potential side. The source of the NMOS transistor N100 is connected in series to the drain of the NMOS transistor N102, while the source of the NMOS transistor N101 is connected in series to the drain of the NMOS transistor N103. Both the drains of the NMOS transistors N100 and N101 are connected to the current source I100, and both the sources of the NMOS transistors N102 and N103 are connected to an NMOS transistor N104 as a load element.
The symbol B100 represents a control signal generator provided with inverters X100, X101, which are CMOS logic circuits. The control signal generator B100 generates (1) a positive phase control signal S for driving one NMOS transistor N100 on the high-potential side and one NMOS transistor N103 on the low-potential side, and (2) a negative phase control signal *S for driving the other NMOS transistor N101 on the high-potential side and the other NMOS transistor N102 on the low-potential side. To state this concretely, the control signal generator B100 inputs an input signal of CMOS level to the inverters X100, X101, and inputs the positive phase control signal S which is output from the inverter X101 to the gate terminals of the NMOS transistors N100, N103, while inputting the negative phase control signal *S which is output from the inverter X100 to the gate terminals of the NMOS transistors N101, N102.
If the input signal is H, the negative phase control signal *S is L and the positive phase control signal S is H. As a result, the NMOS transistors N100, N103 are turned on, while the NMOS transistors N101, N102 are turned off. The current flows from the NMOS transistor N100 toward the NMOS transistor N103 via the transmission line 3, the terminating resistor 5 and the transmission line 4, as indicated by the dotted line, and the LVDS output signal becomes H. On the other hand, if the input signal is L, the negative phase control signal *S is H and the positive phase control signal S is L. As a result, the NMOS transistors N101, N102 are turned on, while the NMOS transistors N100, N103 are turned off. The current therefore flows from the NMOS transistor N101 toward the NMOS transistor N102 via the transmission line 4, the terminating resistor 5 and the transmission line 3, as indicated by the alternate short and long dash line, and the LVDS output signal becomes L. The dc potential is supplied by the voltage which is generated by the NMOS transistor N104 as a load element.
In the conventional structure, there is a phase difference corresponding to one inverter being between the positive phase control signal S and the negative phase control signal *S. Therefore, a time difference is produced between the switching operation of the NMOS transistors N100, N103 which are turned on when the LVDS output is H and the switching operation of the NMOS transistors N101, N102 which are turned on when the LVDS output is L, so that the leading edge and the trailing edge of the LVDS output signal H are asymmetric and the output waveform therefore disadvantageously has a pulse width distortion.
FIG. 14 schematically shows a waveform response which explains such a problem in the related art. There is a phase difference .theta. between the positive phase control signal S and the negative phase control signal *S. For this reason, the timing at which a first current path from the NMOS transistor N100 to the NMOS transistor N103 is turned off does not agree to the timing at which a second current path from the NMOS transistor N101 to the NMOS transistor N102 is turned on. That is, the timing for OFF delays by .theta. corresponding to the phase difference. As a result, there is a period during which both the first and second paths are on. During this period, the LVDS output is not constant, so that the pulse width of the LVDS output is not constant. If the bit rate of an input signal is low, such a pulse width distortion generates little problem, but if the bit rate becomes high, the an exact transmission of a signal becomes remarkable impossible.
In addition, while the NMOS transistor pair N100, N101 on the high-potential side operate in the saturated region, the NMOS transistor N102, N103 pair on the low-potential side operate in the unsaturated region. In the unsaturated region, the switching characteristic is inferior to that in the saturated state, which also leads to a deterioration of the output waveform.
In the normal operation, such a degree of waveform deterioration generates little problem. However, when the noise margin is small, for example, when the LVDS output is used as an output of a optical receiver circuit for amplifying a minute signal level, it is necessary to strictly regulate the pulse distortion of the output waveform.